1. Field of the Invention
This invention relates to a semiconductor memory device, such as an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to an EEPROM that writes and erases the data into and from memory cells by tunnel current.
The invention further relates to such a high-voltage switching circuit as is used in the semiconductor memory device, and more particularly to a voltage switching circuit that uses only NMOS transistors (n-channel MOS transistors).
2. Description of the Related Art
One known type of EEPROMs is a NAND-cell EEPROM capable of high integration. In this type of EEPROM, a plurality of memory cells are connected in series in such a manner that their source and drains may be shared by adjacent cells and these series-connected cells are treated as one unit and connected to a bit line. The memory cells generally have an FETMOS structure in which a charge storage layer (a floating gate) and a control gate are laminated together. The memory cell array is formed by integrating cells in a p-type substrate or p-well. The drain side of a NAND cell is connected to a bit line via a select gate and the source side is connected to a common source line via a select gate. The control gates of the memory cells are arranged consecutively in the row direction and serve as word lines.
The NAND-cell EEPROM operates as follows. The data is written, starting at the memory cell farthest from the bit line (i.e., the memory cell on the source line side). A high voltage V.sub.ppW (=about 18 V) is applied to the control gate of the selected memory cell, an intermediate voltage of V.sub.m10 (=about 10 V) is applied to the control gates of the memory cells closer to the bit line than the selected one and their select gates on the drain side, and 0 V or an intermediate voltage of V.sub.m8 (=about 8 V) is applied to the bit line according to the data.
When 0 V is applied to the bit line, the voltage is transferred to the drain of the selected memory cell, causing electrons to be injected into a charge storage layer. This causes the threshold voltage of the selected memory cell to shift in the positive direction. This state is assumed to be "0", for example. When V.sub.m8 is applied to the bit line, electron injection virtually does not take place and consequently the threshold voltage does not change and remains negative. This state is assumed to be "1" and the erased state. The data is written simultaneously into the memory cells sharing the control gate.
The data is erased in blocks simultaneously from all of the memory cells in the selected NAND cell. All of the control gates in the selected NAND cell block are set at 0 V and the p-well is set at 20 V. At this time, with the high voltage applied to the p-well, the select gate, bit line, and source line are also set at 20 V. This causes the electrons in the charge storage layer to be discharged into the p-well in all of the memory cells in the selected NAND cell block, causing the threshold voltage to shift in the negative direction. All of the control gates of the memory cells in the NAND-cell blocks not to be erased are set at 20 V. High voltages necessary for writing and erasing are generated at the charge pump circuit.
The data is read by setting the control gate of the selected memory cell at 0 V and the control gates and select gates of the other memory cells at a power-supply voltage Vcc (e.g., 3 V), and sensing whether or not current flows through the selected memory cell. To achieve this, the threshold voltage of the memory cell after writing must be Vcc or less.
Since such a NAND-cell EEPROM uses a wide voltage range of 0 V to Vpp (up to 20 V), transistors dealing with a voltage range of 0 V to V.sub.m10 (up to 10 V) (hereinafter, abbreviated as Vm-route transistors) and high-withstand-voltage transistors handling a voltage range of 0 V to Vpp (hereinafter, abbreviated as Vpp-route transistors) are needed. The reason for this is that a circuit to which only a voltage of V.sub.m10 or less is applied is composed of Vm-route transistors of a relatively small size, thereby suppressing the circuit area and only the transistors to which Vpp is applied are determined to be Vpp-route transistors.
This type of device, however, has the following problem.
When n-channel and p-channel MOS transistors are used as Vpp-route transistors, the number of types of transistor increases and production cost rises. When, for example, only n-channel MOS transistors are used as Vpp-route transistors and constitute a circuit, the power-supply voltage cannot be made low because of a decrease in the voltage transfer efficiency due to the threshold voltage of the transistors. Furthermore, when a circuit is composed of, for example, n-channel MOS transistors with a low threshold voltage, acting as Vpp-route transistors, leakage current in the transistors increases the drawn current in the stand-by condition or prevents the high voltage Vpp from being stepped up from the power supply voltage.
Still furthermore, since the writing voltage and erasing voltage are generated internally at the charge pump circuit, variations in production are liable to have an adverse effect on the devices and variations in the threshold voltage after the data has been written into the memory cell must be restricted within a specific range.
Additionally, the above-described semiconductor memory device is provided with a high-voltage switching circuit that switches the high voltage between the selected mode and the unselected mode. With the high-voltage switching circuit, a high voltage is applied to the source of an n-channel MOS transistor (hereinafter, referred to as an NMOS transistor) and a gate voltage is applied to its gate, depending on whether it is in the selected or unselected mode. Specifically, in the selected mode, the gate of the NMOS transistor is applied with the stepped-up voltage, or a high voltage raised from the power supply voltage, the output (drain) is supplied with a boosted voltage higher than the high voltage by at least the threshold voltage of the NMOS transistor so as to achieve complete transfer. In the unselected mode, the gate is applied with the ground.
With the high-voltage switching circuit, although the magnitude of the high boosted voltage required depends on the threshold voltage of the NMOS transistor, the boosted voltage must be made as low as possible to improve the reliability of the transistor. Therefore, the threshold voltage of the NMOS transistor must be made as low as possible. Use of transistors with a low threshold voltage would result in a poorer cut-off characteristic, increasing a leakage current from the high voltage when the high voltage is not transferred. Specifically, even when the output and the gate of the NMOS transistor are grounded, the transistor is not cut off, permitting the input or a leakage current from the high voltage to increase. In this way, because the high voltage is obtained by stepping up the power-supply voltage, as the leakage current increases, a desired high voltage cannot be output.